1) Field
Embodiments of the present invention pertain to the field of Semiconductor Processing and, in particular, to self-aligned double patterning (SADP).
2) Description of Related Art
FIGS. 1A-C illustrate cross-sectional views of a conventional semiconductor lithographic process. Referring to FIG. 1A, a photoresist layer 104 is provided above a semiconductor stack 102. A mask or reticle 106 is positioned above photoresist layer 104. A lithographic process includes exposure of photoresist layer 104 to radiation (hν) having a particular wavelength (λ), as indicated by the arrows in FIG. 1A. Referring to FIG. 1B, photoresist layer 104 is subsequently developed to remove the portions photoresist layer 104 that were exposed to light and thereby provide patterned photoresist layer 108 above semiconductor stack 102. The width of each feature of patterned photoresist layer 108 is depicted by the width ‘x’ of a feature and the space ‘y’ between each feature. The width ‘x’ added to space ‘y’ is referred to as the pitch, p.
Referring to FIG. 1C, the CD, or width ‘x,’ of a feature may be reduced to form patterned photoresist layer 110 above semiconductor stack 102. The CD may be shrunk, or “biased” by over-exposing photoresist layer 104 during the lithographic step depicted in FIG. 1A or by trimming patterned photoresist layer 108 provided in FIG. 1B. However, this reduction in feature CD comes at the expense of an increased spacing between features, as depicted by spacing ‘y’ in FIG. 1C.
The resolution limit for a particular lithographic process is characterized with features having a critical dimension (CD) equal to the space between the features (e.g., x=y, as depicted in FIG. 1B with both x and y being equal to the “half-pitch.”). A conventional 193 nm lithography system may provide a minimum pitch, p, of 130 nm and a 65 nm half pitch. To reduce the effective half pitch of patterns formed in a substrate, density-sensitive integrated circuit (IC) product lines, such as dynamic random access memory (DRAM), are pursuing double patterning (DP). Generally, DP methods successively lithographically pattern a substrate twice with each patterning operation performed with a different mask and a relaxed half-pitch. The two resulting patterns interlace to compose features on the substrate having a half pitch smaller than that of either individual pattern. The composition of the two patterns is then transferred into the substrate to define a pattern in the substrate having a half pitch below that lithographically achievable with the particular lithography employed (e.g., “sub-minimum half-pitch”).
Because DP methods are relatively independent of the lithographic technology employed, they can be practiced with 193 nm lithography as well as high NA or EUV lithography to provide a sub-minimum half pitch. DP methods however are potentially cost prohibitive, particularly as a result of production cycle time, which increases when a DP method employs many additional operations to pattern a particular layer.